1. Field of the Invention
The present invention relates to a level shift circuit, and more particularly, to a level shift circuit which is capable of operating at a low input voltage level.
2. Description of the Prior Art
In general, a level shift circuit is utilized for transiting an input voltage into a different output voltage. Please refer to FIG. 1. FIG. 1 shows a simplified block diagram of a conventional level shift circuit 100 in accordance with a prior art. As shown in FIG. 1, the level shift circuit 100 comprises: a first switch element 110, a second switch element 120, a third switch element 130, and a fourth switch element 140, wherein a voltage level of a first voltage source VN is lower than a voltage level of the second voltage source VP. In addition, the first switch element 110 and the second switch element 120 both are N-type FETs, and the third switch element 130 and the fourth switch element 140 both are P-type FETs, and the level shift circuit 100 is a level pull-up circuit. However, under a condition of the level shift circuit 100 operating at a low input voltage level, a current passing through the third switch element 130 is far greater than a current passing through the first switch element 110 when the first switch element 110 and the third switch element 130 are conducted, and a current passing through the fourth switch element 140 is far greater than a current passing through the second switch element 120 when the second switch element 120 and the fourth switch element 140 are conducted. This phenomenon results in the output voltages having no transitions, and thus level shift circuit 100 is not capable of operating at a low input voltage level.
Please refer to FIG. 2. FIG. 2 shows a simplified block diagram of another conventional level shift circuit 200 in accordance with a prior art. As shown in FIG. 2, the level shift circuit 200 comprises: a first switch element 210, a second switch element 220, a third switch element 230, a fourth switch element 240, a fifth switch element 250 and a sixth switch element 260, wherein a voltage level of a first voltage source VN is lower than a voltage level of the second voltage source VP. In addition, the first switch element 210 and the second switch element 220 both are N-type FETs, and the third switch element 230, the fourth switch element 240, the fifth switch element 250 and the sixth switch element 260 all are P-type FETs, and the level shift circuit 200 is a level pull-up circuit. However, under a condition of the level shift circuit 200 operating at a low input voltage level, a current passing through the third switch element 230 is far greater than a current passing through the first switch element 210 when the first switch element 210 and the third switch element 230 are conducted, and a current passing through the fourth switch element 240 is far greater than a current passing through the second switch element 220 when the second switch element 220 and the fourth switch element 240 are conducted. This phenomenon results in the output voltages having no transitions, and thus level shift circuit 200 is not capable of operating at a low input voltage level.